Forums - Accuracy of simulator

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Accuracy of simulator
martip
Join Date: 17 Jan 17
Posts: 4
Posted: Thu, 2017-03-23 07:45

Hi,

The accuracy of the simulator from Hexagon 2.0 SDK is according to the simulator user guide:

The simulator is not cycle-accurate. With cache modeling enabled it is cycle-
approximate, with current performance within 2% of cycle-accuracy (and
projected performance of less than 1% difference).
My question is, what type of errors is these 2%, random or systematic?
I reran a program multiple times with the simulator and the statistics from the simulator were identical between the runs.
 
A follow-up question is, without cache modeling, what is the accuracy of the simulator?
 
Thanks in advance
 
Best Regards
Martin Persson
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Helu
Join Date: 3 Feb 17
Posts: 8
Posted: Thu, 2017-03-23 08:45

Hi martin,-

​I would think (!) the simulator would be quite deterministic - provided the test data also are the same. And why don't you upgrade the SDK to version 3.1 ?

Thinking about it - if the test data are of random nature then the cache may show quite large variations.
A related topic - is it possible to switch cache modeling on / off by any option?

​BR,
Henrik

 

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martip
Join Date: 17 Jan 17
Posts: 4
Posted: Fri, 2017-03-24 04:58

Hi, and thanks for your quick reply.

I would think (!) the simulator would be quite deterministic - provided the test data also are the same. 

Yes, I would agree on that the simulator seems to be deterministic, which should indicate that there is some systematic error which results in the +-2% stated in the manual.

And why don't you upgrade the SDK to version 3.1 ?

I use the simulator to simulate performance of code for the Hexagon v4 DSP, and I don't see any reason to upgrade. Is there any benefit with the simulator included in SDK 3.1?

A related topic - is it possible to switch cache modeling on / off by any option?

For the simulator provided in SDK 2.0, you can use the --timing argument to simulate caches and processor stalls, 
from the simulator user guide:

--timing:
Model the following processor micro-architecture as part of the simulation:
– Cache (instruction, data, L2)
– Processor stalls
– DMT mode
When timing is enabled, the simulation more accurately models the operation of
the processor hardware. This impacts the speed of the simulation, and improves
the accuracy of the profiling statistics collected

Best Regards
Martin 

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