Hi,
I am trying to write a few bytes of an HVX_Vector to memory using the predicate store instruction - If (Qv4) vmem(Rt) = Vs. However I am getting a compiler error. The details are as below.
Syntax used : if ([!]Qv4) vmem(Rt)=Vs
Code snippet :
HVX_VectorPred Q;
Q= Q6_Q_vsetq_R(0x01); // Set predicate register
HVX_Vector QTmp;
QTmp = Q6_V_vsplat_R(0x00110022); // Set vector to be written to memory
asm("if ([!]%0) vmem(%1) = %2" :: "r"(Q), "+r" (imgDst), "r" (QTmp)); // imgDst is an unsigned char pointer passed from HLOS side
Compiler error report:
getRegForInlineAsmConstraint Unhandled data type
UNREACHABLE executed at /tmp/bots/hexbotmaster-sles11_1/hexagon-clang-80/build/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp:3545!
0 hexagon-clang 0x00000000012a6bc8 llvm::sys::PrintStackTrace(llvm::raw_ostream&) + 40
1 hexagon-clang 0x00000000012a4e06 llvm::sys::RunSignalHandlers() + 70
2 hexagon-clang 0x00000000012a731a
3 libpthread.so.0 0x00002b2603206330
4 libc.so.6 0x00002b2604085c37 gsignal + 55
5 libc.so.6 0x00002b2604089028 abort + 328
6 hexagon-clang 0x000000000126035d llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 461
7 hexagon-clang 0x0000000000857e57 llvm::HexagonTargetLowering::getRegForInlineAsmConstraint(llvm::TargetRegisterInfo const*, llvm::StringRef, llvm::MVT) const + 519
8 hexagon-clang 0x0000000001a4b248
9 hexagon-clang 0x0000000001a28e94 llvm::SelectionDAGBuilder::visitInlineAsm(llvm::ImmutableCallSite) + 4804
10 hexagon-clang 0x0000000001a0c8e0 llvm::SelectionDAGBuilder::visit(llvm::Instruction const&) + 1008
11 hexagon-clang 0x0000000001aaa778 llvm::SelectionDAGISel::SelectBasicBlock(llvm::ilist_iterator<llvm::Instruction const>, llvm::ilist_iterator<llvm::Instruction const>, bool&) + 40
12 hexagon-clang 0x0000000001aaa159 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 11513
13 hexagon-clang 0x0000000001aa5f2e llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1790
14 hexagon-clang 0x000000000082a071
15 hexagon-clang 0x0000000000b35ec5 llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 341
16 hexagon-clang 0x0000000000dc8e84 llvm::FPPassManager::runOnFunction(llvm::Function&) + 564
17 hexagon-clang 0x0000000000dc90cb llvm::FPPassManager::runOnModule(llvm::Module&) + 43
18 hexagon-clang 0x0000000000dc95f3 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 963
19 hexagon-clang 0x000000000144010a
20 hexagon-clang 0x000000000143d4cd clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::DataLayout const&, llvm::Module*, clang::BackendAction, llvm::raw_pwrite_stream*) + 157
21 hexagon-clang 0x0000000001b94e8b
22 hexagon-clang 0x0000000001f79366 clang::ParseAST(clang::Sema&, bool, bool) + 598
23 hexagon-clang 0x000000000183be46 clang::FrontendAction::Execute() + 70
24 hexagon-clang 0x0000000001808c21 clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 1089
25 hexagon-clang 0x00000000018d4421 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 4721
26 hexagon-clang 0x0000000000707bfa cc1_main(llvm::ArrayRef<char const*>, char const*, void*) + 842
27 hexagon-clang 0x000000000070690f main + 11775
28 libc.so.6 0x00002b2604070f45 __libc_start_main + 245
29 hexagon-clang 0x00000000007039f1
Stack dump:
0. Program arguments: /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/tools/HEXAGON_Tools/8.0.10/Tools/bin/hexagon-clang -cc1 -triple hexagon -emit-obj -mrelax-all -disable-free -main-file-name samplemem.c -mrelocation-model pic -pic-level 1 -mthread-model posix -mdisable-fp-elim -mno-zero-initialized-in-bss -relaxed-aliasing -fmath-errno -masm-verbose -mconstructor-aliases -target-cpu hexagonv60 -target-feature +hvx -target-feature +no-small-data -target-cpu hexagonv60 -fno-signed-char -fshort-enums -Wreturn-type -mllvm -enable-quic -mllvm -hexagon-small-data-threshold=0 -D__HEXMSGABI_2_SUPPORTED__ -D__HVX__ -mllvm -enable-hexagon-hvx-double=1 -D__HVX__ -D__HVXDBL__ -mllvm -machine-sink-outside-loop -mllvm -inline-threshold=100 -mllvm -enable-tcm-inline-heuristic=true -mllvm -callee-stack-inline-threshold=512 -v -dwarf-column-info -debug-info-kind=standalone -dwarf-version=4 -debugger-tuning=gdb -fdata-sections -coverage-file /home/rohit.unnimadhavan/Documents/Qualcomm/wd_5.0/openvx-package/openvx12_qdsp/qdspTensor/hexagon_Debug_dynamic_toolv80_v60/samplemem.o -resource-dir /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/tools/HEXAGON_Tools/8.0.10/Tools/bin/../lib/clang/3.9.0 -D __V_DYNAMIC__ -D __FILENAME__="samplemem.c" -D _DEBUG -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/common/qurt//ADSPv60MP/include -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/common/qurt//ADSPv60MP/include/qurt -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/common/qurt//ADSPv60MP/include/posix -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/fastcv/dspCV/hexagon_Debug_dynamic_toolv80_v60/ship -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/test/common/test_util/hexagon_Debug_dynamic_toolv80_v60/ship -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/incs -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/common/remote/ship/hexagon_Debug_dynamic_toolv80_v60 -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/incs/stddef -I /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/libs/common/rpcmem/hexagon_Debug_dynamic_toolv80_v60/ship -I hexagon_Debug_dynamic_toolv80_v60 -internal-externc-isystem /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/tools/HEXAGON_Tools/8.0.10/Tools/bin/../target/hexagon/include -O0 -Wall -Werror -Wno-cast-align -Wpointer-arith -Wno-missing-braces -Wno-strict-aliasing -Wstrict-prototypes -Wnested-externs -fdebug-compilation-dir /home/rohit.unnimadhavan/Documents/Qualcomm/sample -ferror-limit 19 -fmessage-length 205 -fshort-enums -fno-signed-char -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -mllvm -disable-hsdr -o hexagon_Debug_dynamic_toolv80_v60/samplemem.o -x c src/samplemem.c
1. <eof> parser at end of file
2. Code generation
3. Running pass 'Function Pass Manager' on module 'src/samplemem.c'.
4. Running pass 'Hexagon DAG->DAG Pattern Instruction Selection' on function '@hvxSampleMemU8'
hexagon-clang: error: unable to execute command: Aborted (core dumped)
hexagon-clang: error: clang frontend command failed due to signal (use -v to see invocation)
Target: hexagon
Thread model: posix
QuIC LLVM Hexagon Clang version 8.0.10 (based on LLVM 3.9.0)
InstalledDir: /home/rohit.unnimadhavan/Qualcomm/Hexagon_SDK/3.2/tools/HEXAGON_Tools/8.0.10/Tools/bin
hexagon-clang: note: diagnostic msg: Please report the bug through your designated Qualcomm/QuIC support channel.
hexagon-clang: note: diagnostic msg:
********************
Can someone please help me interpret the error report? Is my asm instruction for vmem proper? I have tried the following variants also but without any success.
- asm("if ([!]%0) vmem(%1) = %2" :: "r"(Q), "=r" (imgDst), "r" (QTmp)); // With write permission specified using "=r"
- asm(" vmem(%0)=%1\n" :: "r" (imgDst), "r" (QTmp) ); // Full vector store without any predicate register
Both the above instructions yielded same compiler error as before.
Also, I have modelled my asm instruction for vmem by referring the inline assembly instruction for l2fetch given in downscaleby2 example in Hexagon SDK. If there is any other documentation available regarding inline assembly instructions, it would be great if someone can refer me to that doc.
Cheers,
Rohit
The + means input and output, imgDst is only an input.
This is how you write it.
__asm__ ("if (!%0) vmem(%1) = %2" : : "q"(Q), "r" (imgDst), "v" (QTmp));
The inline assembly is only documented in the 8.2.x tools releases. Next SDK 3.4.0 wil have 8.2.x tools
Regards,
Chenna
Hi Chenna,
Thank you for your kind reply. I tried it the way you suggested and now I am able to compile the instruction properly. :)
However, I have realised that I need to be working with unaligned addresses in order to partial store the vectors in a contiguous fashion. Since the byte enabled store works with aligned addresses, is there any similar method that can be extended for unaligned addresses, in your knowledge?
Also is there any clarity regarding when the next SDK release is planned? Or is there any temporary documentation we can refer till then? I am asking because I would never have guessed the notations like "q", "v" etc, if it was not for your comment.
Thanks,
Rohit
Could anyone shared how to build the HVX example , I have the following build error
I think is my environment setting error, I did not modify the example code and just build it and have the build error following:
I want to used the common HVX example to build the hexagon dilate3x3_C_intrinsics project
following example path : \Hexagon_SDK\3.4.3\examples\common\dilate3x3_v60
but there is error following: