Forums - cmd response change in rising edge is wrong

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cmd response change in rising edge is wrong
huanglei
Join Date: 4 Feb 18
Posts: 4
Posted: Mon, 2018-02-05 00:49

I use 9377-3 sdio module.   3.3V IO. Dell optilex 7050. PCIE->SDIO BOARD.

Found wifi boot fail.  Cmd sometimes wrong. Root cause is cmd response change while sdclk rising, but in fact should latch.

See spec sd spec 3.0. default mode. Tih(input hold time) min=5ns. In fact, it's <2ns.

So cmd sometimes wrong. 

I guess 9377 can change data input change time from rising edge to failing edge.

Who can support it?

 

 

 

Feb  1 10:01:13 PC3039 kernel: [  834.350329] R0: [kworker/1:2][02:01:13.796801]  wlan: [3631:E :VOS] __ol_transfer_bin_file: transferring file: bdwlan30.bin size 8124 bytes done!

Feb  1 10:01:13 PC3039 kernel : [  834.350467] mmc0: starting CMD53 arg 1410a004 flags 000001b5

Feb  1 10:01:13 PC3039 kernel: [  834.350468] mmc0:     blksz 4 blocks 1 flags 00000200 tsac 1000 ms nsac 0

Feb  1 10:01:13 PC3039 kernel: [  834.350490] sdhci [sdhci_irq()]: *** mmc0 got interrupt: 0x00028003

Feb  1 10:01:13 PC3039 kernel: [  834.350500] mmc0: req done (CMD53): -84: 00000000 00000000 00000000 00000000

Feb  1 10:01:13 PC3039 kernel: [  834.350501] mmc0:     4 bytes transferred: 0

Feb  1 10:01:13 PC3039 kernel: [  834.350504] AR6000: SDIO bus operation failed! MMC stack returned : -84 Type your code in the box. To create a new line within the box use SHIFT + ENTER.

Feb  1 10:01:13 PC3039 kernel: [  834.350506] __HIFReadWrite, addr:0X000850, len:00000004, Read , Sync

Feb  1 10:01:13 PC3039 kernel: [  834.350510] Unable to decrement the command credit count register

Feb  1 10:01:13 PC3039 kernel: [  834.350511] BMI : Unable to Send Message to device

Feb  1 10:01:13 PC3039 kernel: [  834.350512] Unable to read from the device

Feb  1 10:01:13 PC3039 kernel: [  834.350514] __ol_transfer_bin_file: Loading setup file qsetup30.bin

Feb  1 10:01:13 PC3039 kernel: [  834.350535] ar6k_wlan mmc0:0001:1: Direct firmware load for qsetup30.bin failed with error -2

Feb  1 10:01:13 PC3039 kernel: [  834.350537] __ol_transfer_bin_file: Failed to get qsetup30.bin:-2

 

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ddeepakk Moderator
Join Date: 27 Jun 17
Posts: 41
Posted: Thu, 2018-02-08 04:57

Hi Huanglei,

What's the SDIO Host Controller you are using?
Meanwhile, let me check if full 3.0 support is enabled for QCA9377 SDIO.

Thanks.

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huanglei
Join Date: 4 Feb 18
Posts: 4
Posted: Thu, 2018-02-08 22:07

I use TI  AM5728 for 9377 evaluation.

According to SD spec, response need to generate by 9377 right after cmd received 2 clk.

I capture waveform from cmd line. I can see 9377 response align rising edge, but spec need be faling edge.

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huanglei
Join Date: 4 Feb 18
Posts: 4
Posted: Thu, 2018-02-08 22:08

I use TI  AM5728 for 9377 evaluation.

According to SD spec, response need to generate by 9377 right after cmd received 2 clk.

I capture waveform from cmd line. I can see 9377 response align rising edge, but spec need be faling edge.

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ddeepakk Moderator
Join Date: 27 Jun 17
Posts: 41
Posted: Sun, 2018-02-11 22:42

Hi Huanglei,

I'm checking internally about your query. Meanwhile could you please help answer below queries from our team:

  1. Regarding “Do we support SD 3.0 fully?”
    [QC] Tufello supports SDIO3.0, am not sure about SD 3.0. Customer is asking SD3.0 or SDIO3.0??
  2. For SDIO3.0 operation, are the Jumper settings set to 1.8V on Tufelllo DUT?
  3. You are using internal power supply or external?
  4. Does the SDIO Controller which you are using support SDIO3.0 1.8V, since below comment of yours talks about 3.3V
    “I use 9377-3 sdio module.   3.3V IO. Dell optilex 7050. PCIE->SDIO BOARD”

>>>>> See spec sd spec 3.0. default mode. Tih(input hold time) min=5ns. In fact, it's <2ns
[QC] Does the SDIO runs at default mode?  Default mode the max clock is 25Mhz. Also, 9377 has no ability to change the clock polarity.

Thanks.

 

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huanglei
Join Date: 4 Feb 18
Posts: 4
Posted: Sun, 2018-02-11 23:03
  1. Regarding “Do we support SD 3.0 fully?”
    [QC] Tufello supports SDIO3.0, am not sure about SD 3.0. Customer is asking SD3.0 or SDIO3.0??

         [HL] SDIO3.0 spec doesn't have timing limitation. SDIO timing say input hold time follow SD3.0 PHY spec.

  1. For SDIO3.0 operation, are the Jumper settings set to 1.8V on Tufelllo DUT?

         [HL] I try both 1.8V & 3.3V IO. Problem happen in HS 3.3V mode, as I say Tih violation .

                   1.8V SDR12 due to host controller issue, not work yet.

    3. You are using internal power supply or external?

         [HL] internel power supply. 1.8V IO come from 3.3V VDD

    4. Does the SDIO Controller which you are using support SDIO3.0 1.8V, since below comment of yours talks about 3.3V
“I use 9377-3 sdio module.   3.3V IO. Dell optilex 7050. PCIE->SDIO BOARD”

        [HL] controller support 1.8V, but sdio host driver not successfully enabled yet.

                 I hope 3.3V can work first, then try 1.8V uhs.

 

Thanks

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ddeepakk Moderator
Join Date: 27 Jun 17
Posts: 41
Posted: Fri, 2018-02-16 06:53

Hi,

Will update you after China holidays.

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