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SPI Communication between qca4020 and stm32 as master
karanpandey844
Join Date: 1 May 20
Posts: 12
Posted: Wed, 2020-06-10 03:01
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Hi,

I am working on qca4020 with 3.1 sdk. I want to communicate between qca4020 and stm32 over spi communication. as per user guide I enabled the  peripheral option as below:

and started module as htc slave spi as 

Peripherals\HTCSlave> 4 1
 
Peripherals\HTCSlave: Start Mailbox Ping test on endpoint 0
Peripherals\HTCSlave: Buffers Per MBOX: 32
Peripherals\HTCSlave: Buffer Size: 256
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Credits Per MBOX: 4
Peripherals\HTCSlave: Start Mailbox Ping test on endpoint 1
Peripherals\HTCSlave: Buffers Per MBOX: 32
Peripherals\HTCSlave: Buffer Size: 256
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Credits Per MBOX: 4
Peripherals\HTCSlave: Start Mailbox Ping test on endpoint 2
Peripherals\HTCSlave: Buffers Per MBOX: 32
Peripherals\HTCSlave: Buffer Size: 256
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Credits Per MBOX: 4
Peripherals\HTCSlave: Start Mailbox Ping test on endpoint 3
Peripherals\HTCSlave: Buffers Per MBOX: 32
Peripherals\HTCSlave: Buffer Size: 256
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Max Message Size: 2048
Peripherals\HTCSlave: Credits Per MBOX: 4
 
Peripherals\HTCSlave>
 

now in slave side there are 6 pin as MOSI,MISO,SCK,CS,INTR.

 

In Host side i generated code using stm32cubemx for spi communication which is giving only three pins as

MOSI,MISO,SCK and one GPIO pin i selected as CS pin which I am toggeling(HI/LOW) before and after sending data.this process is not working there is nothing happening in slave side.

and I am not getting any idea what is interrupt(INTR) pin in slave side. and how to control it from host(stm32) side.

 Please help me asap.

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Re: SPI Communication between qca4020 and stm32 as master
c_rpedad
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Join Date: 18 Jun 18
Location: San Jose
Posts: 317
Posted: Thu, 2020-07-30 11:38
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The demo uses mailbox, hence INTR pin is used to enable interrupt going from SPI core to Mailbox.
Interrupt will be generated for error conditions and packet available within read buffer.SPI core to Mailbox.

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