Forums - SPI master issue

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SPI master issue
flexeos
Join Date: 7 Feb 19
Posts: 12
Posted: Thu, 2019-03-21 07:46
Hi all
 
We are evaluating QCA4020 for a new design
 
To start development and investigate module capabilities we bought QCA4020 development kit from Qualcomm
 
Our design requires QCA4020 acting as an SPI master to communicate with an external device
 
We noticed that system is strongly unstable and subject to malfunction especially regarding to SPI signals. We noticed that in many cases clock and MOSI behaviour is not correct. It seems that not all bytes are transferred. Randomly some bytes are skipped during transmission. We noticed that the module is dramatically sensitive to noise on ground net
 
We started from QCLI Demo adding spi master capability since we didn't find any complete example, so we are not sure about all the settings, especially for pinmuxing. How can we set the pins to use SPI master properly? Is there an example project to use SPI as a master (not HTC)?
 
Thanks in advance
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gesqdn-forum
Join Date: 4 Nov 18
Posts: 184
Posted: Tue, 2019-03-26 22:47

Hi flexeos,

The device qca4020 is well supported for SPI communication.

We used  Serial communication between two boards, QCA4020 and  Dragonboard 410c.


There are options provided in QCLI Demo for SPI and SPI Master, kindly check those if you are not aware.
You can find the SPI API guide from "4.10 SPI Master" section in https://developer.qualcomm.com/download/qca4020-qca4024/qca402x-qapi-specification.pdf?referrer=node/35653

If you can let us know how can we help you.

 

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flexeos
Join Date: 7 Feb 19
Posts: 12
Posted: Wed, 2019-03-27 06:14

Hi

I found this workaround for the SPI in the code of the QCLI_demo (file spi.hal.c)

Is there a more exhaustive documentation of the problem and how to cope with it?

 

Thanks in advance

 

 

/*
* WORKAROUND:
*
* On some motherboards, whether SPI target is connected or not,
* the SPI transactions for accessing SPI target registers are found to
* stall.
*
* Quartz doesn't suppport hotplug for SDIO/SPI. And the assumption is
* mutliple (currently two) targets are statically wired during boot.
*
* Also the Host APIs doesn't identity the transport to initialize.
*
* Hence a timed bail out, gracefully handles the initialization sequence
* SPI transactions.
*/

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