Hi,
in the documentation it is mentioned that L2 Data Cache Prefecth can be performed by using the L2fecth instruction.
It is also mentioned that the User Status register needs to be read/set to enable L2 Cache Prefetches.
There is no source code I could find in the Hexgon SDK package to enable or read the USR w.r.t. L2 cache.
Could anyone share some info on this.
Thanks.
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